1. Field of the Invention
The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly to a resistance change type semiconductor memory device and a method of manufacturing the same.
2. Description of the Related Art
Semiconductor memory devices having various kinds of structures such as a Dynamic Random Access Memory (DRAM) and a Static Random Access Memory (SRAM) are known as semiconductor memory devices. In addition, semiconductor memory devices having various kinds of structures are known as non-volatile semiconductor memory devices as well.
A resistance change type semiconductor memory device as one of the non-volatile semiconductor memory devices is described in a Non-Patent Document 1 of K. Aratani et al., Proceeding of 2007 IEEE International Electron Devices Meeting pp. 787 to 786 (2007). In addition, the resistance change type semiconductor memory device having the same structure as that of the resistance change type semiconductor memory device described in a Non-Patent Document 1 is described in Japanese Patent Laid-Open No. 2006-173267 (referred to as Patent Document 1) as well.
FIG. 9 is a schematic cross sectional view showing a structure of a resistance change type semiconductor memory device according to the related art.
In a semiconductor substrate 110, an active region is divided into parts by an isolation insulating film (not shown). Also, a Metal-Oxide-Semiconductor (MOS) transistor is formed in a region (not shown).
Referring to FIG. 9, a first insulating film 111 is formed on the semiconductor substrate 110, and a region of the first insulating film 111 connected to the semiconductor substrate 110 or the like is opened. Also, a plug-like first electrode 112, for example, made of W or the like is filled in the region having the opening portion formed therein. The plug-like first electrode 112 is formed so as to be connected to a source/drain region of the MOS transistor described above, and has a function as a lower layer wiring.
A resistance change type memory layer 113 is formed on the first electrode 112 as an upper layer, and an ion source layer 114 is formed as an upper layer on the resistance change type memory layer 113.
For example, a third insulating film 115 is formed on the ion source layer 114, an opening portion is formed in the third insulating film 115 so as to reach the ion source layer 114, and a second electrode 116 is filled in the opening portion of the third insulating film 115.
For example, the ion source layer 114 contains therein both an element selected from the group including Cu, Ag and Zn, and an element selected from the group including Te, S and Se.
In addition, the memory layer 113 is made of either any one of a tantalum oxide, a niobium oxide, an aluminum oxide, a hafnium oxide, and a zirconium oxide, or a mixed material thereof.
For manufacturing the semiconductor memory device having the structure described above, for example, the first insulating film 111 is formed on the semiconductor substrate 110 having the isolation insulating film formed therein. The opening portion is formed in the first insulating film 111 so as to open a portion which is intended to be connected to the source/drain region of the MOS transistor, and the plug-like first electrode 112 is filled in the portion having the opening portion formed therein to be formed in the opening portion.
The resistance change type memory layer 113 is formed as the upper layer on the plug-like first electrode 112 by, for example, utilizing a physical vapor deposition method, a chemical vapor deposition, or the like, and the ion source layer 114 is formed as the upper layer on the memory layer 113.
For example, the third insulating film 115 is formed on the ion source layer 114, the opening portion is formed in the third insulating film 115 so as to reach the ion source layer 114, and the second electrode 116 is formed within the opening portion.
In the manufacturing method described above, the memory layer 113 made of a thin film is formed on the first electrode 112 composed of the W plug and the like. Here, a surface of the first electrode 112 composed of the W plug and the like is not flat, and a stepped portion exists between a peripheral insulating film and the first electrode 112. For this reason, it is difficult to thin the memory layer while the step coverage property is ensured. Thus, with regard to the element resistance and the memory characteristics, the thinning of the memory layer causes the dispersion among the elements.
On the other hand, it is previously found out that when the memory layer 113 is thickened in order to increase a film quality, a voltage necessary in a phase of recording is increased. Thus, a low voltage operation of the memory becomes difficult to carry out, and thus the thickening of the memory layer 113 causes an increase in chip size.